1. Field of the Invention
The present invention relates to a solid-state imaging device and a driving method thereof, which are used in image inputting apparatuses (e.g., video cameras, electronic cameras (digital cameras), image inputting cameras, scanners, facsimile machines, etc.), and the like.
2. Description of the Related Art
Conventionally, semiconductor image sensors, such as CCD-based image sensors, MOS-based image sensors, and the like, have been used as solid-state imaging devices. Such semiconductor image sensors are employed in most image inputting apparatuses. Particularly, the merits of MOS-based image sensors are recently recognized once again, i.e., that the power consumption is low and they can be fabricated with the same CMOS techniques as those used for peripheral circuits thereof.
Such a recent trend in technology is shown in, for example, Japanese Laid-Open Publication No. 11-195778 (Japanese Patent No. 2935492), which discloses a modified MOS-based image sensor (solid-state imaging device). This is a threshold voltage modulating MOS-based image sensor which has a carrier pocket region (high-concentration buried region) below a channel region of an optical signal detecting MOS transistor. This MOS-based image sensor will be described with reference to FIG. 11.
FIG. 11 is a cross-sectional view showing a unit pixel portion of a conventional MOS-based image sensor 20H.
In the MOS-based image sensor 20H, a plurality of unit pixel portions 3H are arranged in a matrix. Each unit pixel portion 3H has a light receiving diode 1H for photoelectric conversion, and an optical signal detecting MOS transistor 2H (insulated gate field effect transistor) adjacent thereto. Adjacent unit pixel portions 3H are separated from each other by a field oxide film 4. The light receiving diode 1H and the MOS transistor 2H are provided within a P-type well region 5H.
The light receiving diode 1H has a P-type well region 51H (a portion of the P-type well region 5H), in which electric charges are generated due to photoelectric conversion, and an N-type impurity diffusion region 6 provided on an upper surface of the P-type well region 51H. The N-type impurity diffusion region 6 is buried in the P-type well region 51H.
The MOS transistor 2H has a gate electrode 21, an N-type source region 22, an N-type drain region 23, a channel region 24 in which electric charges are transferred, and a P-type hole pocket region 25.
The gate electrode 21 is provided via a gate insulating film (not shown) on the P-type well region 5H. The gate electrode 21 is in the shape of a ring, when viewed from the top.
The N-type source region 22 is located inside the annular gate electrode 21 and on an upper surface of the P-type well region 5H. The N-type source region 22 functions as a source diffusion region.
The N-type drain region 23 is provided on the upper surface of the P-type well region 5H, surrounding the outer circumference of the annular gate electrode 21. The N-type drain region 23 functions as a drain diffusion region. The N-type drain region 23 is in the shape of a ring, when viewed from the top. The N-type drain region 23 is integrated with the N-type impurity diffusion region 6. An end portion of the outer circumference of the N-type impurity diffusion region 6 is connected to an N-type well region 7H which surrounds the P-type well region 5H.
The channel region 24 is located below the gate electrode 21 and on the upper surface of the P-type well region 5H between the N-type source region 22 and the N-type drain region 23. The channel region 24 is provided as an N-type impurity region (N-type impurity layer).
The P-type hole pocket region 25 is located below the gate electrode 21 and within the P-type well region 5H near the N-type source region 22, surrounding the N-type source region 22. The P-type hole pocket region 25 is in the shape of a ring, when viewed from the top. The P-type hole pocket region 25 is provided as a P-type high-concentration buried region having an impurity concentration higher than that of the P-type well region 5H.
The P-type well region 5H is provided within the N-type well region 7H on a P-type semiconductor substrate 8. The N-type well region 7H is separated from other N-type well regions 7H adjacent thereto via the above-described field oxide film 4 and the P-type separation region 9.
A basic operation of the MOS-based image sensor 20H will be described with reference to a timing chart of FIG. 12. The MOS-based image sensor 20H performs a series of imaging operations, i.e., an initializing (discharging) operation, an accumulating operation, and a reading operation.
As shown in FIG. 12, during a discharging period, the drain voltage VD of the drain region 23 and the gate voltage VG of the gate electrode 21 are set to be as high as about 5 V for initialization. In this case, the potential of the source region 22 is also set to be about 5 V via the channel region 24. The potential distribution of the device 20H during the discharging period is shown in FIG. 13.
FIG. 13 is a diagram showing the potential distribution of the device 20H along a plane passing through the hole pocket region 25 in a direction (depth direction) perpendicular to the substrate surface, during the discharging period. The vertical axis represents a potential value, while the horizontal axis represents a depth (distance) from the upper surface of a unit pixel portion.
Referring to FIG. 13, the potential values of the gate insulating film, the N-type (N+) channel region 24, the P-type (P+) hole pocket region 25, the P-type well region 5H, the N-type well region 7H, and the P-type semiconductor substrate 8 vary from the gate voltage VG (5 V) to GND (0V).
According to such a potential distribution, substantially all electric charges (holes) accumulated in the hole pocket region 25 are discharged to the P-type semiconductor substrate 8.
Next, during an accumulation period, the drain voltage VD is reduced to 3 V as shown in FIG. 12. In this case, electric charges are generated by photoelectric conversion within the P-type well region 51H of the light receiving diode 1H. In this case, the gate voltage VG is reduced to 1 V. Thereby, the MOS transistor 2H is turned off, so that electric charges (holes) are accumulated in the hole pocket region 25 which has the lowest potential.
Further, during a reading period, a constant current source is connected to the source region 22, and the drain region 23, the gate electrode 21 and the source region 22 form a source follower circuit. In this case, the gate voltage VG is increased to 3 V to operate the MOS transistor 2H at a saturated state thereof. In this case, the source potential is modulated depending on the amount of electric charges accumulated in the hole pocket region 25. By reading a signal indicating such a modulation, the amount of incident light can be detected. FIG. 14 shows a potential distribution during the reading period.
FIG. 14 is a diagram showing the potential distribution of the device 20H along a plane passing through the hole pocket region 25 in a direction (depth direction) perpendicular to the substrate surface, during the reading period. The vertical axis represents a potential value, while the horizontal axis represents a depth (distance) from the upper surface of a unit pixel portion.
Referring to FIG. 14, the potential values of the gate insulating film, the N-type (N+) channel region 24, the P-type (P+) hole pocket region 25, the P-type well region 5H, the N-type well region 7H, and the P-type semiconductor substrate 8 vary from the gate voltage VG (3 V) to GND (0V).
The potential value of the hole pocket region 25 and the P-type well region 5H is lower than that of the N-type well region 7H. Therefore, the N-type well region 7H functions as a potential barrier between the P-type well region 5H and the P-type semiconductor substrate 8, so that electric charges are accumulated in the hole pocket region 25. In FIG. 14, a hatched portion indicates the maximum amount of electric charges which can be accumulated in the hole pocket region 25.
In the MOS-based image sensor 20H, electric charges accumulated in the hole pocket region 25 need to be completely discharged to the P-type semiconductor substrate 8 during a discharging period. In order to keep the N-type well region 7H from being a barrier against discharging of electric charges to the P-type semiconductor substrate 8, the potential of the hole pocket region 25 needs to be higher than that of the N-type well region 7H.
To achieve such a potential distribution, it is necessary to use a voltage (5 V in the embodiment of FIGS. 12 and 13) higher than operation voltages (1 V and 3 V in the embodiment of FIGS. 12 and 13). Such a high voltage can be obtained by providing a specialized power supply externally or a booster circuit having a capacitor inside a chip. When a booster circuit is provided inside a chip, the area of the chip is increased because a capacitor or the like is required. In addition, it may be necessary to construct a process for manufacturing a transistor which withstands a high voltage.